Every four years, the Pacific Rim Meeting on Electrochemical and Solid-State Science (PRiME) conference brings together leading industry players to discuss a diverse blend of electrochemical and solid-state science and technology. The conference also serves as one of the largest Pacific Rim forums for the discussion of our interdisciplinary research. This international gathering is the joint effort of The Electrochemical Society, The Electrochemical Society of Japan and The Korean Electrochemical Society, with the technical co-sponsorship of the Chinese Society of Electrochemistry, the Electrochemistry Division of the Royal Australian Chemical Institute, The Japan Society of Applied Physics, the Korean Physical Society Semiconductor Division and the Semiconductor Physics Division of the Chinese Physics Society.
This year, Dow Electronic Materials has been invited to present on “Copper Plating and Its Application in Advanced Packaging,” a paper co-authored by Lucy Wei, Matthew Thorseth, Mark Scalisi, Jonathan Prange, Inho Lee, Yil-Hak Lee, Yoon Joo Kim, Mark Lefebvre, Jeff Calvert and Wataru Tachikawa. Part of the electrodeposition track in the G04 session on processing materials of 3D interconnects, damascene and electronics packaging, the paper explores materials challenges for advanced electronic packaging metallization, and looks ahead to Dow’s next-generation copper pillar chemistry.
Tuesday, October 4, 2016: 13:40
304 B (Hawai'i Convention Center)
Conventional acid electroplated copper is being widely used in semiconductor industries from back-end-of-the-line interconnects to advanced packaging applications such as copper pillar, redistribution layer copper and through silicon via (TSV) because of low cost, easy manufacturing process and high throughput. Industry trends toward higher-performance semiconductor devices with increased interconnect density have created significant materials challenges for advanced electronics packaging metallization processes. Copper pillar becomes a transformative technology replacing traditional controlled collapse chip connection bumps to meet new performance demands.
Copper pillar chemistry requires innovative organic additives in order to meet challenges such as flat pillar shape, void-free intermetallic interface after reflow with solder, fast plating speed, high-purity deposits and excellent uniformity. Copper plating baths may contain at least one of the three additives: accelerator, suppressor and leveler. Accelerator is usually used to enhance plating rate (depolarization agent), just as its name indicates, while suppressor and leveler are polarization agents that inhibit the plating locally. Although all the additives can be defined as either polarization or depolarization agents, depending on the electrochemical response, the function of each additive could be very different depending on the application.
In this talk, the additive function in three different electroplating applications, dual damascene, TSV and copper pillar, will be compared. We will then introduce the development of Dow Electronic Materials’ next-generation copper pillar chemistry. Additives, current density and process impact on plating performance will be discussed.