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Showing all articles related to Fan out wafer-level packaging

IMAPS Device Packaging Conference to Feature Next-Gen Materials and Trends

February 28, 2017

At this year’s IMAPS Device Packaging Conference, Dow experts will present sessions on Integrated Packaging and Substrate Technologies for Next-Generation Smart Devices, and Integration of Chemically Amplified Photoresist and High-Speed Copper Plating Products for Advanced Packaging Technologies.

Copper Electroplating Fundamentals

November 22, 2016

This tutorial examines the concept of copper electroplating and how the process works. It also discusses its use in advanced packaging applications like the dual damascene process, TSV, copper pillars, and copper RDL, as well as how feature geometry as well as plating time affect how additives behave.

Dow’s Rozalia Beica to Present at the SEMICON Taiwan SiP Global Summit

August 23, 2016

The SiP Global Summit, which takes place during SEMICON Taiwan, is a two-day workshop devoted to advancements in system-in-package technologies. As part of this year’s novel material and equipment readiness segment of the program, Dow’s Rozalia Beica will tackle the challenges of both embedded technologies and fan-out wafer-level packaging.

Fast, High-purity Cu Plating Enables Next-Gen Devices

April 20, 2016

Copper (Cu) plating of mega pillar

Fan-out wafer-level packages (FOWLP) are poised for adoption in consumer mobile devices while cloud servers are driving the need for 3DIC packages. Copper (Cu) plating forms critical connections from horizontal redistribution layers (RDLs) through vertical pillars. Learn more about Dow’s approach to optimal Cu plating, as presented at the 2016 IMAPS Device Packaging Conference.

Join Dow at the 2016 IMAPS Device Packaging Conference

March 03, 2016

IMAPS Device Packaging Conference 2016 in Fountain Hills Arizona

Dow Electronic Materials will be participating in this year’s IMAPS Device Packaging Conference with other industry leaders to move forward a number of advanced packaging technologies. Dow will present two papers in the Interposer and 3D-IC & Packaging track and contribute to a third presented by Fraunhofer IZM.

Advanced Packaging Materials Adding More Value to ICs

January 22, 2016

Solid State Technology logo

Dow Electronic Materials’ Rob Kavanagh takes a look at the state of materials for advanced packaging in his 2016 Outlook now featured on Solid State Technology.

Self-Priming Low Stress Aqueous Developable Benzocyclobutene Photodielectric Materials for Advanced Wafer Level Packaging

August 18, 2015

Photoimageable polymeric dielectric materials are in need of modification to meet the warpage targets for thinned 300mm wafers used in fan-out wafer level packages, where lower residual stress is required. This presentation discusses a prototype dielectric material developed by Dow’s Advanced Packaging Technologies group that meets these requirements.