Dow Electronic Materials will be back for another annual installment of the IMAPS Device Packaging Conference. Together with industry leaders and experts, Dow will be there to do its part to move forward a number of advanced packaging technologies—including system-in-package (SiP), embedded die, fan-out wafer-level packaging (FOWLP), 2.5D and 3D integration—that are now getting the credit they are due for the value they add to semiconductor devices. That means 2016 should be an exciting year to attend the conference, which takes place March 15-17, 2016 at the We-Ko-Pa Resort and Conference Center in Fountain Hills, Arizona. This year’s technical program looks to be another good one with 14 sessions featuring more than 80 speakers in 4 topic tracks: interposers, 3D IC and packaging; FOWLP and flip chip; engineered micro systems/devices (including MEMS & sensors); and new this year—a SiP track all its own. Dow Electronic Materials will be presenting two papers in the Interposer and 3D-IC and Packaging track and contributing to a third paper presented by Fraunhofer IZM:
Tuesday, March 15 at 4:00 p.m.
TP1: 3D Device Fabrication Processes, Materials and Yield
Evaluation of High-Speed Copper Plating Products for RDL, Micropillar, and Fan-Out Applications
Matthew Thorseth, Mark Scalisi, Inho Lee, Sang-Min Park, Yil-Hak Lee, Jonathan Prange, Masaaki Imanari, Mark Lefebvre, Jeff Calvert, Dow Electronic Materials, Advanced Packaging Technologies
Flip-chip interconnects that enable advanced packaging utilize a C4 bumping process with lead-free solder to make the chip interconnection. However, with the decreasing chip size and tighter I/O pitch requirements needed to realize high-performance, the industry is turning to Cu pillar plating to meet the technical demands, and as such, a significant increase in Cu pillar capacity is anticipated. In this paper, Cu electroplating products are evaluated for plating performance at increased deposition rates for Cu pillar applications ranging from micropillar (<20 µm feature size), to standard pillar (20-75 µm feature size), redistribution layer (RDL) wiring, and the emerging fan-out wafer-level packaging (FOWLP), which encompasses megapillars (>150 µm feature sizes) as well as stacked via RDL designs.
Wednesday, March 16 at 2:00 p.m.
WP1: 3D Device Fabrication Processes, Materials and Yield
Non-Conductive Film (NCF) Underfill: Materials, Performance, and Evolution to Next-Generation Devices
Edgardo Anzures, Paul Morganelli, Robert Barr, Jeffrey Calvert, Avin Dhoble, David Fleming, Jong-Uk Kim, Herong Lei, Dow Electronic Materials, Advanced Packaging Technologies, in collaboration with Juergen Grafe, Julian Haberland, Fraunhofer IZM
As 3D chip stacking increasingly becomes a requirement, non-conductive film (NCF) underfills will play a critical role in the assembly process. NCF underfills, applied as a film laminated to a wafer, offer significant advantages over capillary underfills and other underfill technologies for fine-pitch designs. Additionally, there have been major advances in the development and mechanistic understanding of NCF technology over the past few years, to the extent that it has now evolved to multiple materials developed to accommodate varying design parameters. This paper will present the development and test results of initial NCF technology applied to a base test vehicle with 1,000 I/O copper pillars and the evolution to the next-generation NCF materials for high I/O die assembly (36,000 I/Os).
Wednesday, March 16 at 2:30 p.m.
WP1: 3D Device Fabrication Processes, Materials and Yield
Laser Direct Patterning of Dry Etch BCB Adhesive Layers for Low-Temperature Permanent Wafer-to-Wafer Bonding
K. Zoschke, M. Wegner, M. Töpper, Fraunhofer IZM and K-D. Lang, Technical University of Berlin, in collaboration with M. Gallagher, R. Barr, J. Calvert, J.-U. Kim, Dow Electronic Materials,
To enable advanced wafer-level packaging approaches for devices like MEMS, image sensors or optical elements, wafer-to-wafer bonding processes using structured, low-temperature, curable adhesives are required. Many studies of benzocyclobutene (BCB)-based wafer bonding have shown the material’s broad range of applications and good performance in addition to some of its limitations, , such as long bond cycles and high cure temperature of 250°C. New process concepts have resulted in a reduction in wafer bond cycles to less than 10 minutes and a post-bond batch cure at temperatures below 200°C. This collaborative paper reviews the new BCB wafer bond processes for supporting short cycle times, with special focus on the new patterning approach by laser ablation. Process flow description as well as systematic analysis of pattern reproducibility of the new structuring method are part of the discussion.
Rounding out Dow’s participation in the technical program, Jeff Calvert will serve as technical co-chair for the Interposers, 3D IC & Packaging track while Eric Huenger will service as technical co-chair for the Flip Chip, Wafer Level Packaging & FAN-OUT track.
In addition to these presentations, Dow will be exhibiting at the show in booth #29. Please stop by to learn more about our entire advanced packaging portfolio and how we support next-generation manufacturing.