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Showing all articles related to Capped Cu Pillar

Copper Pillar Electroplating Tutorial

December 08, 2016

This tutorial examines the requirements and processing considerations for electroplated copper pillars used in advanced chip packaging applications. The key aspects of the plating process and the role of each in achieving the desired design and performance goals are described.

Does Electrodeposited Indium have a Future in Advanced Packaging?

May 04, 2016

Low temperature bonding using electrodeposited indium

Copper (Cu) pillars are important interconnect structures used in advanced IC packaging, requiring cost-effective solder capping materials, and lower bonding temperature is emerging as an important driver. This article provides an overview of “Enabling Low-Temperature Bonding in Advanced Packaging using Electrodeposited Indium,” to be presented at the 2016 ECTC sponsored by IEEE.

Fast, High-purity Cu Plating Enables Next-Gen Devices

April 20, 2016

Copper (Cu) plating of mega pillar

Fan-out wafer-level packages (FOWLP) are poised for adoption in consumer mobile devices while cloud servers are driving the need for 3DIC packages. Copper (Cu) plating forms critical connections from horizontal redistribution layers (RDLs) through vertical pillars. Learn more about Dow’s approach to optimal Cu plating, as presented at the 2016 IMAPS Device Packaging Conference.

Wafer Bumping Considerations: The importance of the interface between metal layers

March 15, 2016

Capped pillar – intermetallic compound compatibility, metal layer interface

Many new assembly processes are in development, including ultra thinning of wafers to enable stacked die, package-on-package (PoP) and ultra-thin packages. Wafer-level packaging (WLP) to improve reliability and I/O count, ball pitch and routability are also imperative. This post provides an introduction on materials considerations for the interface between metal layers in wafer bump structures.

Dow’s SOLDERON™ Tin-Silver Plating Chemistry Takes Home an Oscar of Innovation

November 23, 2015

R&D 100 Winner banner for SOLDERON Tin-Silver Plating Chemistry

It’s been a banner year for SOLDERON™ BP TS 6000 Tin-Silver Plating Chemistry, which was recently awarded an R&D; 100 Award, presented by R&D; Magazine in a ceremony at Caesar’s Palace in Las Vegas. This “Oscar of Innovation” takes its place in Dow Electronic Materials’ trophy case, next to the 2015 Edison Award.

Three Dow Electronic Materials Technologies Named Finalists for 2015 R&D; 100 Awards

August 19, 2015

Dow was recently highlighted as a leading innovator with 21 products selected as finalists for the 2015 R&D 100 Awards. Three of these are technologies developed by Dow Electronic Materials as market-focused solutions and commercialized in the last year.

Next-Generation Copper, Nickel and Lead-Free Metallization Products for Next-Generation Devices and Applications

August 15, 2015

Meeting the challenging requirements of next-generation devices destined for Internet of Things applications necessitates metallization products that can address fine feature sizes and geometries of today’s advanced chip and package designs. This presentation details how Dow Electronic Materials has optimized its family of advanced electronics packaging metallization products.

How Do Tin-Silver Caps Influence Reliability of Copper Pillar Applications?

July 23, 2015

As packaging technologies must address the higher performance and increased functionality of today’s electronic devices, traditional C4 bumps are reaching their limits. The industry is turning to Cu pillars as a solution for fine pitch bumping, with tin-silver caps becoming the solder capping material of choice. In this interview, Dr. Jianwei Dong explains why.

3D TSV Plating and Bumping: Rising to the Challenge

July 22, 2015

TSVCopperCropped

3D integration using through silicon vias (TSVs) promises a fundamental shift for current multi-chip integration and packaging approaches, but it brings more difficulties in Cu electroplating. This piece explores process and material optimization efforts to enable volume manufacturing of 3D ICs.

Solving Data Center Reliability Challenges through Packaging

July 07, 2015

The semiconductor industry is approaching a point where 2.5D and 3D integration technologies will be required to achieve the performance, bandwidth and storage required of next-generation data centers and mobile devices. In this piece, Wataru Tachikawa explores how the entire ecosystem is rolling up its sleeves and working to overcome the remaining challenges.